Course Information Package
|Course Unit Title||DIGITAL SYSTEM DESIGN|
|Course Unit Code||AEEE561|
|Course Unit Details||PhD Computer Science (Postgraduate level courses) - MSc Electrical Engineering (Required Courses) - PhD Electrical Engineering (Postgraduate level courses) -|
|Number of ECTS credits allocated||7|
|Learning Outcomes of the course unit||By the end of the course, the students should be able to:|
|Mode of Delivery||Face-to-face|
|Recommended optional program components||NONE|
Verilog: Top-Down Design. File organization. Modules. Structural and Behavioural Description. Verilog Primitives. Concurrent and sequential statements. Tasks and functions. Include files and design for reuse.
Verification: Basic verification methodology. Verilog testbenches: directed and constrained-random testing, self-checking testbenches using behavioural HDLs.
ASIC architectures and Implementation Options: Synthesis and EDA tools for ASIC and FPGA emplementation. Semi-custom / full custom ASICs. Gate Array, Standard Cell, Full Custom. CMOS/BI-CMOS technologies. PLDs and FPGAs.
Digital Systems Design - ASMs: ASMs, Mealy and
ASIC/VLSI design for testability: Testing, verification and production. Design for Testability (DFT). Built-in self-test, signature analysis.
Laboratory work: Individual or small group experiments using VHDL, FPGA implementation and testing.
|Recommended and/or required reading:|
|Planned learning activities and teaching methods|
The course is structured in lectures that are conducted with the help of both computer presentations and traditional means. Practical examples and exercises are included in the lectures to enhance the material learning process. Often short post-lecture quizzes are used to assess the level of student understanding and provide feedback. Student questions are addressed during the lecture, or privately after the lecture or during office hours. Lectures include tutorials of EDA tools and design case studies.
Lecture notes are available through the web for students to use in combination with the textbooks.
Students are assessed continuously and their knowledge is checked through tests with their assessment weight, date and time being set at the beginning of the semester via the course outline.
Furthermore, guided individual and group design assignments are used to develop practical engineering skills while integrating the course theory.
Laboratory experiments are carried out in small groups and lab reports are required two weeks after the laboratory class resulting in a cumulative mark. The first laboratory exercises are totally structured (cookbook) in order to familiarize the students with the equipment, while later exercises are less structured, allowing the student to create their own designs or programs for a given application.
|Assessment methods and criteria|
|Language of instruction||English|