MSc in Electrical Engineering
Course Information Package
|Course Unit Title||DIGITAL SYSTEM VERIFICATION AND TESTING|
|Course Unit Code||AEEE576|
|Course Unit Details||PhD Computer Science (Postgraduate level courses) - MSc Electrical Engineering (Technical Electives) - PhD Electrical Engineering (Postgraduate level courses) -|
|Number of ECTS credits allocated||7|
|Learning Outcomes of the course unit||By the end of the course, the students should be able to:|
|Mode of Delivery||Face-to-face|
|Recommended optional program components||NONE|
Introduction to verification concepts and guidelines: Verification Plan - First-Time Success - ASIC and FPGA Verification - System-Level Verification - Board-Level Verification - Verification Strategies
Directed and constrained-random verification: Simple Stimulus - Verifying the Output - Self-Checking Testbenches - Input and Output Vectors - Predicting the Output
Verification with SystemVerilog: Procedural Statements - Tasks, Functions, and Void Functions - Local Data Storage - Time Values
Testbench components: Generator, agent, driver, scoreboard, monitor and checker – Connecting the DUV.
Randomization and coverage: What to Randomize - Randomization in SystemVerilog - Constraint Details - Coverage Types - Functional Coverage Strategies - Data Sampling
Introduction to testing: Test economics, cost-benefit analysis – economics of testable design
Fault modelling: Defects, errors and faults – single stuck-at faults – fault collapsing
Design for testability and Built-In-Self-Test (BIST): Scan methods – BIST using LFSRs.
|Recommended and/or required reading:|
|Planned learning activities and teaching methods|
Students are taught the course through lectures (3 hours per week) in classrooms or lectures theatres, by means of traditional tools or using computer demonstration.
Auditory exercises, where examples regarding matter represented at the lectures, are solved and further, questions related to particular open-ended topic issues are compiled by the students and answered, during the lecture or assigned as homework.
Topic notes are compiled by students, during the lecture which serve to cover the main issues under consideration and can also be downloaded from the lecturer’s webpage. Students are also advised to use the subject’s textbook or reference books for further reading and practice in solving related exercises. Tutorial problems are also submitted as homework and these are solved during lectures or privately during lecturer’s office hours. Further literature search is encouraged by assigning students to identify a specific problem related to some issue, gather relevant scientific information about how others have addressed the problem and report this information in written or orally.
Students are assessed continuously and their knowledge is checked through tests with their assessment weight, date and time being set at the beginning of the semester via the course outline.
Students are prepared for final exam, by revision on the matter taught, problem solving and concept testing and are also trained to be able to deal with time constraints and revision timetable.
The final assessment of the students is formative and summative and is assured to comply with the subject’s expected learning outcomes and the quality of the course.
|Assessment methods and criteria|
|Language of instruction||English|