Course Information Package
|Course Unit Title||ADVANCED COMPUTER ARCHITECTURE|
|Course Unit Code||AEEE564|
|Course Unit Details||PhD Computer Science (Postgraduate level courses) - MSc Electrical Engineering (Required Courses) - PhD Electrical Engineering (Postgraduate level courses) -|
|Number of ECTS credits allocated||7|
|Learning Outcomes of the course unit||By the end of the course, the students should be able to:|
|Mode of Delivery||Face-to-face|
|Recommended optional program components||NONE|
Issues raised and tradeoffs in modern high performance processor and computer designs. Latency tolerance and technology trends and limitations
Instruction Level Parallelism: Complex Pipelines, superscalar, superpilelined, VLIW/EPIC and Vector microarchitectures and OOO execution. Branch prediction and Speculative execution.
Thread Level Parallelism: Latency and latency tolerance. Multithreading, implicit/explicit multithreading, blocking/non-blocking multithreading, and thread switching mechanisms.
Technology Issues: Clock frequency trends, transistor density trends, power scaling and temperature issues, wire scaling, wire fan out and soft errors.
Chip multiprocessors and tiled architectures and multi-core processors. The cache coherence problem and cache coherence protocols. CMP interconnects and networks-on-chip.
|Recommended and/or required reading:|
|Planned learning activities and teaching methods||
Students are taught the course material through lectures by means of electronic presentation slides. Homework problems are assigned to strengthen students’ knowledge and understanding.
Students are requested to prepare a literature review assignment and a paper review related on advanced work published. Furthermore, students need to prepare and debate in the class on a topic related to the forefront of computer architecture in the context of the course.
|Assessment methods and criteria|
|Language of instruction||English|