BSc in Computer Science / Бакалавр в Области Компьютерных Наук

Course Details

Course Information Package

Course Unit TitleCOMPUTER ARCHITECTURE I
Course Unit CodeACOE201
Course Unit Details
Number of ECTS credits allocated7
Learning Outcomes of the course unitBy the end of the course, the students should be able to:
  1. Describe the instruction execution cycle with reference to the flow of information at the register level, and analyse typical Instruction Set Architectures with respect to the number of operands, addressing modes and branch types.
  2. Describe the internal structure and operation of a CPU datapath and design a simple single-cycle and a multi-cycle non-pipelined CPU.
  3. Describe the internal structure of the types of semiconductor memory devices, evaluate them with respect to memory capacity, speed and power consumption, and design memory modules.
  4. Explain how the memory wall problem affects the performance of a computer and how cache memory exploits locality to reduce the memory wall problem.
  5. Describe the operation and evaluate the performance of the common cache memory mapping methods, cache replacement policies and write policies.
  6. Explain the function of virtual memory mechanisms, and analyse the mechanisms found in modern high performance microprocessors that support virtual memory.
  7. Use EDA tools, VHDL code and FPGA boards to design, simulate, verify, implement and test the operation of datapath units, a simple CPU, memory devices and a simple cache unit.
Mode of DeliveryFace-to-face
PrerequisitesACOE161Co-requisitesNONE
Recommended optional program componentsNONE
Course Contents

Introduction to computer organization and architecture: Instruction cycle and flow of information at the register level. Instruction Set Architectures, instruction formats and instruction decoding. Relation between machine language, assembly language and high level languages.

CPU design basics: Datapaths, register files, ALU, shift and rotate circuits. Register transfer operations and micro-operations. Control unit implementation, hardwired control and microprogrammed control. Single-cycle and multi-cycle non-pipelined CPU design.

Semiconductor Memory: Internal structure of semiconductor memory devices, signals and basic characteristics. Types of memory devices, ROM (masked, programmable, flash) and RAM (dynamic and static). Memory expansion and memory addressing.

Memory Hierarchy: The memory wall problem and the locality principle. Cache memory organization and mapping. Cache replacement and write policies. Cache performance metrics. Virtual memory.

Laboratory Work: Individual or small group experiments performed with the use of common FPGA boards and VHDL. Experiments include the design and analysis of the basic units of a typical CPU such as register files, ALUs, memory devices and simple cache units.

Recommended and/or required reading:
Textbooks
  • M. Mano, C. R. Kime, Logic and Computer Design Fundamentals, Prentice Hall, 2010
References
  • Paterson, Hennessy, Computer Organization and Design: the Hardware/Software Interface, Morgan Kaufman, 2008
Planned learning activities and teaching methods

The taught part of course is delivered to the students by means of lectures, conducted with the help of computer presentations. Lecture notes and presentations are available through the web for students to use in combination with the textbooks.

Lectures are supplemented with laboratory work carried out on FPGA boards. During laboratory sessions, students develop the functional units, taught in the lecture sessions, in schematic and VHDL description, download them on an FPGA board and verify their operation.
Assessment methods and criteria
Assignments10%
Tests30%
Laboratory work20%
Final Exam40%
Language of instructionEnglish
Work placement(s)NO

 Печать  E-mail