Course Details
Course Information Package
Course Unit Title | HIGH PERFORMANCE PROCESSOR ARCHITECTURE | ||||||||||
Course Unit Code | ACOE455 | ||||||||||
Course Unit Details | |||||||||||
Number of ECTS credits allocated | 5 | ||||||||||
Learning Outcomes of the course unit | By the end of the course, the students should be able to:
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Mode of Delivery | Face-to-face | ||||||||||
Prerequisites | ACOE301 | Co-requisites | NONE | ||||||||
Recommended optional program components | NONE | ||||||||||
Course Contents | Issues raised and tradeoffs in modern high performance processor and computer designs. Latency tolerance and technology trends and limitations Instruction Level Parallelism: Complex Pipelines, superscalar, superpilelined, VLIW/EPIC and Vector microarchitectures and OOO execution. Branch prediction and Speculative execution. Thread Level Parallelism: Latency and latency tolerance. Multithreading, implicit/explicit multithreading, blocking/non-blocking multithreading, and thread switching mechanisms. Simultaneous multithreading, hyperthreading, Subordinate Multithreading SSMT/Helper threads. Technology Issues: Clock frequency trends, transistor density trends, power scaling and temperature issues, wire scaling, wire fan out and soft errors. Chip multiprocessors and tiled architectures and multi-core processors. The cache coherence problem and cache coherence protocols. CMP interconnects and networks-on-chip. | ||||||||||
Recommended and/or required reading: | |||||||||||
Textbooks |
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References |
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Planned learning activities and teaching methods | The course is delivered to the students by means of lectures, conducted with the help of computer presentations. Lecture notes and presentations are available through the web for students to use in combination with the textbooks. | ||||||||||
Assessment methods and criteria |
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Language of instruction | English | ||||||||||
Work placement(s) | NO |