BSc in Computer Engineering / Бакалавр в Області Комп'ютерної Інженерії

Course Details

Course Information Package

Course Unit TitleHIGH PERFORMANCE PROCESSOR ARCHITECTURE
Course Unit CodeACOE455
Course Unit Details
Number of ECTS credits allocated5
Learning Outcomes of the course unitBy the end of the course, the students should be able to:
  1. Explain the effect and limitations of semiconductor technology on modern microarchitectures, with respect to the clock frequency, power consumption, heat dissipation and transistor size
  2. Apply ILP techniques on single-core pipelined, superscalar, VLIW and multithreaded microarchitectures and employ optimizations such as branch prediction and out-of-order execution.
  3. Describe the memory hierarchy optimizations found in high performance processors and employ cache optimizations such as multilevel caches, software and hardware prefetching, victim caches, etc.
  4. Employ thread-level parallelism on multi-core microarchitectures such as SMT, chip-multiprocessors and tiled architectures.
  5. Explain how modern microarchitecture optimizations are employed by current high performance processors.
  6. Use appropriate performance metrics and employ the performance monitoring registers of high performance processor to monitor, evaluate and improve their performance.
Mode of DeliveryFace-to-face
PrerequisitesACOE301Co-requisitesNONE
Recommended optional program componentsNONE
Course Contents

Issues raised and tradeoffs in modern high performance processor and computer designs. Latency tolerance and technology trends and limitations

Instruction Level Parallelism: Complex Pipelines, superscalar, superpilelined, VLIW/EPIC and Vector microarchitectures and OOO execution. Branch prediction and Speculative execution.

Thread Level Parallelism: Latency and latency tolerance. Multithreading, implicit/explicit multithreading, blocking/non-blocking multithreading, and thread switching mechanisms. Simultaneous multithreading, hyperthreading, Subordinate Multithreading SSMT/Helper threads.

Technology Issues: Clock frequency trends, transistor density trends, power scaling and temperature issues, wire scaling, wire fan out and soft errors.

Chip multiprocessors and tiled architectures and multi-core processors. The cache coherence problem and cache coherence protocols. CMP interconnects and networks-on-chip.

Recommended and/or required reading:
Textbooks
  • Paterson, Hennessy, Computer Architecture: a Qualitative Approach, Morgan Kaufman, 2010
References
  • Processor Manuals and scientific publications
Planned learning activities and teaching methods

The course is delivered to the students by means of lectures, conducted with the help of computer presentations. Lecture notes and presentations are available through the web for students to use in combination with the textbooks.

Assessment methods and criteria
Assignments10%
Tests30%
Class Project20%
Final Exam40%
Language of instructionEnglish
Work placement(s)NO

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