MSc in Electrical Engineering

Course Information Package

Course Unit CodeAEEE564
Course Unit DetailsPhD Computer Science (Postgraduate level courses) - MSc Electrical Engineering (Required Courses) - PhD Electrical Engineering (Postgraduate level courses) -
Number of ECTS credits allocated7
Learning Outcomes of the course unitBy the end of the course, the students should be able to:
  1. Explain how high performance microarchitectures employ instruction-level-parallelism, thread-level-parallelism and chip-level-parallelism to improve the performance of a computer.
  2. Evaluate computer hardware units in terms of performance, latency, heat, and hardware budget requirements.
  3. Propose and justify optimizations in the context of Instruction-level-parallelism, thread-level-parallelism and chip-level-parallelism that can improve the performance of a computer.
  4. Analyse the effects of semiconductor technology issues such as clock frequency, transistor density, power and temperature issues, and soft errors on the evolution of computer microarchitecures.
  5. Outline the basic features of chip multiprocessors and relate them with modern high performance processors.
  6. Review, present and evaluate published information related to the forefront of computer architecture.
Mode of DeliveryFace-to-face
Recommended optional program componentsNONE
Course Contents

Issues raised and tradeoffs in modern high performance processor and computer designs. Latency tolerance and technology trends and limitations

Instruction Level Parallelism: Complex Pipelines, superscalar, superpilelined, VLIW/EPIC and Vector microarchitectures and OOO execution. Branch prediction and Speculative execution.

Thread Level Parallelism: Latency and latency tolerance. Multithreading, implicit/explicit multithreading, blocking/non-blocking multithreading, and thread switching mechanisms.

Technology Issues: Clock frequency trends, transistor density trends, power scaling and temperature issues, wire scaling, wire fan out and soft errors.

Chip multiprocessors and tiled architectures and multi-core processors. The cache coherence problem and cache coherence protocols. CMP interconnects and networks-on-chip.


Recommended and/or required reading:
  • Paterson, Hennessy, Computer Architecture: a Qualitative Approach, Morgan Kaufman, 2010
  • Students are expected to consult a variety of information sources, including processor manuals, and scientific and research papers.
Planned learning activities and teaching methods

Students are taught the course material through lectures by means of electronic presentation slides. Homework problems are assigned to strengthen students’ knowledge and understanding.

Students are requested to prepare a literature review assignment and a paper review related on advanced work published. Furthermore, students need to prepare and debate in the class on a topic related to the forefront of computer architecture in the context of the course.

Assessment methods and criteria
Mid-term Exam 20%
Literature Review Assignment15%
Paper Review Assignments15%
Class Debate 10%
Final Exam40%
Language of instructionEnglish
Work placement(s)NO