MSc in Electrical Engineering

Course Information Package

Course Unit CodeAEEE562
Course Unit DetailsPhD Computer Science (Postgraduate level courses) - MSc Electrical Engineering (Required Courses) - PhD Electrical Engineering (Postgraduate level courses) -
Number of ECTS credits allocated7
Learning Outcomes of the course unitBy the end of the course, the students should be able to:
  1. Show how data and instructions are encoded and manipulated at the hardware level, with respect to non-pipelined and pipelined datapaths.
  2. Design and analyse complex digital circuits required for the implementation of the functional units of computer hardware.
  3. Propose and justify optimizations that can improve the performance of a computer in terms of Instruction Level Parallelism.
  4. Evaluate computer hardware units in terms of performance, latency, heat, and hardware budget requirements.
  5. Describe the operation and evaluate the performance of the common cache memory mapping methods, cache replacement policies and write policies.
  6. Analyse optimizations and techniques employed in modern high performance processor that improve the performance of a cache system
  7. Explain the function of virtual memory mechanisms, and analyse the mechanisms found in modern high performance microprocessors that support virtual memory.
Mode of DeliveryFace-to-face
Recommended optional program componentsNONE
Course Contents

The course aims to introduce MSc-level students to advanced concepts in uniprocessor computer organization and architecture.

Instruction Set Architecture (ISA): Specifications, classes, registers, memory addressing and addressing modes. MIPS assembly language. The MIPS, 80x86, and EPIC ISAs.

Performance: Measuring performance and metrics. Benchmarks, performance monitoring and hardware performance counters. Software performance monitoring and software tuning tools.

Single Cycle CPU Design: Princeton and Harvard style architectures. Datapath design to support data manipulation, data transfer and control instructions. Control unit design. Hardwired vs microprogramming, RISC vs CISC architectures.

Pipelining: Pipeline design issues, hazards and optimizations such as forwarding, loop unrolling, branch prediction, register renaming, speculative execution, and out-of-order execution.

Memory hierarchy: The memory wall problem. Semiconductor memory optimizations, locality and memory hierarchy. Advanced cache memory and cache optimizations such as multilevel caches, software and hardware prefetching, thread level prefetchers, victim caches. Virtual memory, protection, and translation.


Recommended and/or required reading:
  • Paterson, Hennessy, Computer Organization and Design: the Hardware/Software Interface, Morgan Kaufman, 2010
  • Paterson, Hennessy, Computer Architecture: a Qualitative Approach, Morgan Kaufman, 2010
Planned learning activities and teaching methods

Students are taught the course material through lectures by means of electronic presentation slides. Homework problems are assigned to strengthen students’ knowledge and understanding.

Students are requested to prepare a literature review assignment and a paper review related on advanced work published. Furthermore, students need to prepare and debate in the class on a topic related to the forefront of computer architecture in the context of the course.

Assessment methods and criteria
Mid-term Exam 20%
Literature Review Assignment15%
Paper Review Assignments15%
Class Debate10%
Final Exam40%
Language of instructionEnglish
Work placement(s)NO